One recent innovation in circuit design methodology has been the development of the so-called "domino" and cascode voltage switch family of logic circuits. Domino logic circuits increase speed performance by electrically precharging a series of logic gates during a first clock phase, and then evaluating the intended logic function during the next clock phase. The critical speed path is pipelined in domino logic circuits so that one portion of the domino gates is precharging while another portion is evaluating. Examples of CMOS domino logic circuits are found in U.S. Pat. Nos. 5,517,136, 4,700,086 and 5,369,621. Various techniques for enhancing speed performance in CMOS domino logic circuits are further described in U.S. Pat. Nos. 5,121,003, 5,208,490 and 5,343,090.
As feature sizes of CMOS process technology shrinks, current density, power consumption and clock loading become significant problems in logic circuit design. Consider the traditional domino logic circuit shown in FIG. 1. Domino logic circuit 100 comprises a first domino gate (D1) that provides an output that drives a second domino gate (D2), and so on down the chain. Each domino logic gate consists of two main components: a precharge p-type field-effect device having its gate coupled to an input clock signal, and a conditional pull-down n-type device stack that evaluates a set of inputs. the case of the D1 domino gate, the p-type pull-up device 101 is shown being coupled between the positive supply, V.sub.cc, and output node 115. The n-channel device stack 112 is coupled in series with clocked n-type transistor 114 between node 115 and ground. The inputs to be evaluated by device stack 112 are denoted by signal lines A.sub.0 -A.sub.N. The D2 domino gate is similarly arranged, with a p-type device 121 being coupled between V.sub.cc and node 125. N-channel device stack 122 having inputs B.sub.0 -B.sub.M is coupled in series with n-type device 124 between node 125 and ground. An additional input is provided at node 120, generated by the D1 gate at output node 115 via inverter 117. Likewise, the D2 output provided at node 125 is coupled through inverter 127 to node 127.
As mentioned above, the device stack is utilized to evaluate the input logic signals. Included in the device stack is an n-type field-effect device coupled in series between the n-type transistors and ground, with the gate of the n-type device also being coupled to a clock signal.
Operation of the traditional domino logic circuit 100 of FIG. 1 is relatively simple. When the clock signal coupled to the gates of devices 101, 114,121 and 124 is low, the pipeline circuitry is in a precharge phase. Domino output nodes 115 and 125 are precharged to a high potential during this precharge phase. The signal levels of inputs A.sub.0 -AN and B.sub.0 -B.sub.M are unimportant during the precharge stage, since the n-type devices coupled between the output nodes (115 and 125) and ground are nonconducting, i.e., "off". When the clock signal transitions high, domino output nodes 115 and 125 are no longer actively driven by the p-type field-effect pull-up device. In the case where the inputs A.sub.0 -A.sub.N satisfy certain logic conditions, the output node 115 is discharged and the input to the second domino gate transitions high. Similarly, if input node 120 and inputs B.sub.0 -B.sub.M satisfy certain logic conditions, output node 125 is discharged and node 129 transitions high. Thus, when the clock signal (CLK) is high, the domino logic circuit is in an evaluation phase.
It should be appreciated that the input signals to the domino gates should be stable or monotonically rising during the evaluation phase, otherwise the domino nodes may be discharged incorrectly.
There are several problems with the traditional domino logic circuitry of FIG. 1. First of all, a clock signal (or its complement) triggers all the precharge devices, which loads the clock lines severely. Furthermore, there is a large current spike in the power network when the domino logic gate enters the precharge phase due to all of the precharge devices being synchronized by the clock edge pulse. This requires a very robust power network and decoupling capacitors may be required. In addition, race conditions may exist when the domino pipeline chain drives a static latch. For example, if output node 129 enters a high-phase latch, which is open when the clock is high, then when the clock transitions low, precharged values may override the latch data if the latch turns off late.
Thus there is a need for an improved domino logic pipeline circuit that overcomes the drawbacks of the prior art.